A transmission apparatus in a wireless communication system includes a power amplifier for amplifying power of transmission signals. The power amplifier is required to operate in a region as close to saturation as possible in order to improve the power efficiency. However, the relationship between the linearity and the power efficiency of the power amplifier is trade-off. Thus, the transmission apparatus includes a distortion compensation apparatus in order to simultaneously improve the linearity and the power efficiency. The distortion compensation apparatus is used for the purpose of suppressing non-linear distortion generated in the power amplifier during a high efficiency operation and for lowering an ACLR (Adjacent Channel Leakage Ratio) due to the non-linear distortion outside a band (out-of-band) and an EVM (Error Vector Magnitude) due to non-linear distortion inside the carrier band (in-band).
One scheme used in the distortion compensation apparatus is a DPD (Digital Predistortion) scheme. A distortion compensation apparatus of the DPD system adds in advance a signal having an inverse characteristic of a non-linear distortion of a power amplifier to an input signal of the power amplifier to improve the linearity of the output signal of the power amplifier to thereby suppress output distortion.
The output distortion of the power amplifier includes not only distortion due to memoryless non-linearity that depends only on an input signal at a certain time but also distortion due to a memory effect which occurs because of a bias current and an input signal at the timing shifted from the input signal at the certain time. Furthermore, the memory effect of the power amplifier becomes more noticeable as the bandwidth of the input signal increases, which limits the performance of the DPD.
Proposed specific signal processing performed by the DPD to compensate the distortion due to the memory effect include inverse distortion generation processing based on series-based methods such as Volterra Series, Memory Polynomial, and Generalized Memory Polynomial.
The DPD based on the Volterra series has a problem that it is highly difficult to implement it on actual hardware, because the complexity of the DPD increases exponentially in some cases. In order to address this problem, for example, NPL (Non Patent Literature) 1 (D. R. Morgan, Z. Ma, J. Kim, M. G. Zierdt, and J. Pastalan, “A generalized memory polynomial model for digital predistortion of RF power amplifiers”, IEEE Transactions on Signal Processing, vol. 54, no. 10, pp. 3852-3860, October 2006) and NPL 2 (3GPP TR 38.803, V14.1.0 (2017-June), Technical Report, “3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Study on new radio access technology: Radio Frequency (RF) and co-existence aspects”, Annex A: PA models) propose a memory polynomial structure and a generalized memory polynomial structure. The memory polynomial structure is a simplified Volterra series for the purpose of minimizing a coefficient amount that is in a trade-off relationship with compensation performance. The generalized memory polynomial structure generalizes and extends a time shift amount of a memory effect term for an input signal at a certain time not only to a lagging term but also to a leading term in order to improve the performance of the memory polynomial structure.
As hardware for achieving the memory polynomial model and the generalized memory polynomial structure, commonly, a signal processing apparatus that performs a calculation equivalent to a power series using a look-up table (LUT) has been proposed. Further, for example, NPL 2 proposes a generalized memory polynomial model representing a specific non-linear model of a power amplifier based on an actual measurement or a circuit simulation. However, in the generalized memory polynomial model disclosed by NPL 2, it is necessary to derive an inverse system for an extremely large number of non-linear model coefficients, at the maximum of 8 (non-linear order: 0 to 7)×7(memory order: 7)×2 (I phase Q phase: 2)=112. Thus, the generalized memory polynomial model disclosed by NPL 2 has a problem in which even when signal processing is performed based on a simplified generalized memory polynomial structure, an extensive amount of the calculation is still required, which is a first problem in the related art.
Next, a problem involved in changes in technology trends will be described.
3rd Generation Partnership Project (3GPP) has been studying standardization of the preceding release 5G (5th Generation) Phase 1 in order to achieve large capacity communication in a 5G wireless communication system. However, even in 5G Phase 1, it is required to widen the band from 5 times to 20 times larger than that of the existing 4G (4th Generation). In particular, 800 MHz is required as the maximum system bandwidth in the quasi-millimeter wave/millimeter wave band.
In 5G Phase 1, it is agreed to aggregate carriers by the same Intra-band Contiguous Carrier Aggregation to achieve the system band of 800 MHz in the quasi-millimeter wave/millimeter wave band. For example, eight carriers each having a channel bandwidth (Ch BW: Channel Bandwidth) of 100 MHz with a sub-carrier spacing (SCS) of 60 kHz, the number of sub-carriers 1500 to 1584, and an FFT size of 2048 could be aggregated. Alternatively, four carriers each having a channel bandwidth of 200 MHz with a sub-carrier spacing of 60 kHz, the number of sub-carriers 3000 to 3168, and an FFT size of 2048 could be aggregated. Further alternatively, two carriers each having a channel bandwidth of 400 MHz with a sub-carrier spacing of 120 kHz, the number of sub-carriers of 3000 to 3168, and an FFT size of 4096 could be aggregated. However, when the system band 800 MHz is achieved by aggregating carriers by the same in-band continuous carrier aggregation as described above, an operation at an extremely high sampling frequency of 983.04 MHz is required in order to process the baseband signal in a total of 800 MHz band after the carriers are aggregated, even when the distortion is not compensated.
For example, when the above processing of the baseband signal is achieved by an FPGA (Field Programmable Gate Array), the maximum operating frequency (called Fmax.) exceeding 1 GHz in the FPGA is a prospective value that can be reached in the next 7 nm or 5 nm onward, which will be released in the future. Thus, under the condition in which the FPGA of the current process is used, it is necessary to employ a two-phase poly-phase structure also for the operation at 983.04 MHz when the above-mentioned distortion compensation is not performed, and to operate a chain of each phase at ½ of the above sampling frequency of 983.04 MHz.
In a trend of 5G standardization for quasi-millimeter wave/millimeter wave band, 3GPP has been discussing to introduce a scale for ACLR of a BS (Base Station) and ACIR (Adjacent Channel Interference Ratio) by ACS (Adjacent Channel Selectivity of UE (User Equipment) to loosen the ACLR standard for the BS. As a result, 3GPP has agreed at the present time that the ACLR standard of the BS in the frequency band of 24 GHz or higher is loosened to 28 dBc (24.24 to 33.4 GHz band) and 26 dBc (37 to 52.6 GHz band). For this reason, there is a possibility of achieving the system band of 800 MHz only for the ACLR standard due to non-linear distortion outside the carrier band (out-of-band) in the quasi-millimeter wave/millimeter wave band even when the distortion compensation is not to be performed.
However, the influence on the EVM (error vector amplitude) remains in terms of the non-linear distortion within the carrier band (in-band). In order to satisfy the EVM standard 3.5% at the time of 256 QAM (Quadrature Amplitude Modulation) including an influence of phase noise of a local (locally oscillated) signal for a radio circuit in the quasi-millimeter wave/millimeter wave band and EVM degradation involved in an influence of a signal peak factor reduction signal of a signal, it is necessary to achieve roughly 40 dBc as an SNR (Signal to Noise Ratio) distribution by non-linear distortion within the carrier band. Thus, in particular, distortion compensation for compensating the non-linear distortion within the carrier band is required.
When the distortion is compensated, commonly, k-order non-linearity generates a distortion component occupying a bandwidth k times as large as a modulation bandwidth of an input signal (=a maximum frequency of an amplitude envelope change of the input signal). For this reason, a DPD that compensates this distortion component over the entire band needs to operate at a sampling frequency k times the modulation band of the input signal. For example, an operating frequency (a sampling frequency) of approximately 4 GHz is required for a DPD that compensates for up to fifth order non-linearity for a input signal band of 800 MHz in the quasi-millimeter wave/millimeter wave band. Further, even when the compensation is limited to third order non-linearity, an operating frequency of approximately 2.4 GHz is required for a DPD. Therefore, the system requirement for the operating frequency of the DPD exceeds the performance trend of an achieved device, which is a second problem in the related art.
Next, specific problems of the related art will be described with reference to the drawings.
FIG. 8 is a block diagram showing a configuration of the distortion compensation apparatus according to the related art in the transmission apparatus.
As shown in FIG. 8, the distortion compensation apparatus includes a DPD (digital predistorter) 1, a DA (digital-to-analog) converter 2, a transmission upconverter 3, a power amplifier 4, a directional coupler 5, a feedback downconverter 6, an AD (analog-to-digital) converter 7, and an interpolation circuit 8.
An input signal (a baseband signal) x(n) of the distortion compensation apparatus is upsampled by the interpolation circuit 8 at the upstream of the DPD 1, and the upsampled xu(n) is input to the DPD 1. The upsampling by the interpolation circuit 8 increases a sampling rate (a sampling frequency) of the input signal x(n) to expand a band of a digital signal for distortion compensation in the DPD 1. It is determined how many times higher the operating frequency (the sampling frequency) of the DPD 1 should be than the modulation band of the input signal x(n) based on a multiplication factor of the upsampling by the interpolation circuit 8.
Note that the technique of up sampling an input signal of the DPD at the upstream of the DPD and outputting the upsampled signal to the DPD is disclosed in, for example, U.S. Pat. Nos. 9,209,753 and 8,537,041. Hereinafter, the distortion compensation apparatus for up sampling the input signal of the DPD at the upstream of the DPD is referred to as an upsampling distortion compensation apparatus as appropriate. In the upsampling distortion compensation apparatus, the DPD for inputting the upsampled input signal at the upstream thereof is referred to as an upsampling DPD as appropriate.
For example, assume that the xu(n), which has been up sampled by the interpolation circuit 8 twice the original sampling rate for the sampling frequency 983.04 MHz, which is necessary for processing the above-described input signal x(n) in the 800 MHz band in the quasi-millimeter wave/millimeter wave band, is input to the DPD 1. In this case, the operating frequency of the DPD 1, i.e., the band of the digital signal for distortion compensation, is 1.96608 GHz, which is 2.4576 times the band 800 MHz of the input signal x(n).
The DPD 1 performs processing (distortion compensation processing) for generating yu(n), in which a signal having an inverse characteristic of the non-linear distortion of the power amplifier 4 is added in advance to the input upsampled xu(n), and then outputs the generated yu(n) to the DA converter 2. Details of the DPD 1 will be described later.
The DA converter 2 converts the output signal yu(n) of the DPD 1 from a digital signal to an analog signal, and outputs the converted analog signal to the transmission upconverter 3.
The transmission upconverter 3 upconverts the analog signal from the DA converter 2 to an RF (Radio Frequency) signal, and outputs the upconverted RF signal to the power amplifier 4.
The directional coupler 5 feeds back a part of the RF signal amplified and output by the power amplifier 4 and outputs it as a feedback RF signal for an output observation. The feedback RF signal obtained by the directional coupler 5 is fed back to the DPD 1 via the feedback downconverter 6 and the AD (analog-to-digital) converter 7.
The feedback downconverter 6 downconverts the feedback RF signal from the directional coupler 5, and outputs the downconverted signal to the AD converter 7.
The AD converter 7 converts the signal from the feedback downconverter 6 from an analog signal to a digital signal, and feeds back the converted digital signal as a feedback signal zu(n) to the DPD 1.
The DPD 1 performs the distortion compensation processing using the feedback signal zu(n) from the AD converter 7. Specifically, the DPD 1 includes an LUT, and updates the LUT according to the feedback signal zu(n). Then, in the distortion compensation processing, the DPD 1 calculates a signal having an inverse characteristic of the non-linear distortion of the power amplifier 4 using the updated LUT, and adds the calculated signal to xu(n) to thereby generate yu(n). Details of the LUT will be described later.
Recently, an interpolation DAC is used (hereinafter, the DA converter 2 is referred to as an interpolation DA converter 2 as appropriate) as the DA converter 2 in FIG. 8 for the purpose of eliminating the need to correct an image due to a DC offset and a quadrature error resulting from imperfection of an analog quadrature modulator and for simplifying a radio circuit. The interpolation DA converter is a DA converter that incorporates an interpolation function and a Digital Quadrature Modulator function.
Note that the above-described interpolation DA converter is used not only for the purpose of achieving the above digital quadrature modulation but also as a DA converter even when digital orthogonal modulation is not performed. For example, the above-described interpolation DA converter can alleviate the performance requirement of an analog filter that is necessary for an output part of the DA converter. The above-described interpolation DA converter is commonly used not only as a discrete DA converter but also as a DA converter incorporated in general-purpose ICs for specific applications requiring miniaturization and integration for the purpose of performing over sampling which exerts a miniaturizing effect.
For example, NPL 3 (V. Leung, and L. Larson, “Improved Digital-IF Transmitter Architecture for Highly Integrated W-CDMA Mobile Terminals”, IEEE Transactions on Vehicular Technology, vol. 54, no. 1, pp. 20-32, January 2005) disclose the above-described digital orthogonal modulation scheme.
FIG. 9 is a block diagram showing a function example of the interpolation DA converter 2.
The interpolation DA converter 2 is configured to achieve the digital quadrature modulation function in a manner described below. First, the interpolation DA converter 2 is operated at a sampling clock rate four times the sampling frequency of input I and Q signals to interpolate each of the input I and Q signals to four times the sampling frequency. A complex multiplier 206 complex-multiplies the I signal interpolated to four times the sampling frequency by a sine signal for an I phase (e.g., 0, 1, 0, −1, 0, . . . ) from a NCO (Numerical Controlled Oscillator) 205. A complex multiplier 207 complex-multiplies the Q signal interpolated to four times the sampling frequency by a cosine signal for a Q phase (e.g., 1, 0, −1, 0, 1, . . . ) from the NCO 205. Then, the signals complex-multiplied by the complex multipliers 206 and 207 are added by an adder 208 to obtain a digital quadrature modulated signal. After that, this digital quadrature modulated signal is converted into an analog signal by one (single channel) DA converter 209. Then, a quadrature modulated real IF signal having an IF (Intermediate Frequency) frequency of ¼ the sampling clock rate of the interpolation DA converter 2 is output.
Here, the interpolation DA converter 2 includes two stages of 2× interpolation circuits for performing zero-stuffing on an input signal of each stage, and then eliminating an image with a half-band filter for interpolation to thereby achieve a 4-fold interpolation function.
The above half-band filter is used when an application for processing multirate signals interpolates the multirate signal to twice the original sampling rate or decimates the multirate signal to ½ the original sampling rate. The above half-band filter is implemented in a polyphase form, because about half of the coefficients are equal to zero.
The interpolation DA converter 2 incorporates, as an upstream (first stage) 2× interpolation circuit, a half-band filter1 201 and a half-band filter1 202 for the first stage 2× interpolation, and as a downstream (second stage) interpolation circuit, a half-band filter2 203 and a half-band filter2 204 for the downstream 2× interpolation circuit. These half-band filters are for interpolation of 80% a Nyquist passband. Commonly, the half-band filter1 201 and the half-band filter1 202 for the first stage 2× interpolation are FIR (Finite Impulse Response) filters of about 59 taps, and the half-band filter2 203 and the half-band filter2 204 for the downstream 4× interpolation are FIR filters of about 23 taps.
By employing the interpolation DA converter 2, the transmission upconverter 3 at the downstream of the interpolation DA converter 2 only needs to convert the real IF signal output from the interpolation DA converter 2 into an RF signal, which eliminates the need for an analog quadrature modulator. Thus, when the interpolation DA converter 2 is employed, it is possible to achieve an effect in which a radio circuit can be simplified, and processing for correcting an image due to a DC offset and a quadrature error resulting from imperfection of an analog quadrature modulator can be deleted.
In the distortion compensation apparatus according to the related art shown in FIG. 8, assume that the interpolation circuit 8 is deleted and the upsampling for the DPD 1 is not performed for the purpose of reducing the operating frequency of the DPD 1 itself in order to address the above-described second problem concerning the device performance. With this configuration, as shown in FIG. 14 (a detailed description will be given later), for example, the operating frequency of the DPD 1 for the input signal band of 800 MHz in the quasi-millimeter wave/millimeter wave band remains as 983.04 MHz, which is necessary for processing the above-described input signal x(n) in the 800 MHz band and which is only 1.2288 times the band of the input signal x(n).
Next, it will be described how difficult it is to achieve a configuration in which the interpolation circuit 8 is deleted as assumed above with reference to the related art for a comparison.
Commonly, the AD converter has a relatively lower sampling rate than that of the DA converter, and becomes a rate-limiting factor in terms of performance. Thus, for example, NPL 4 (Y. Liu, W. Pan, S. Shao, and Y. Tang, “A New Digital Predistortion for Wideband Power Amplifiers With Constrained Feedback Bandwidth,” IEEE Microwave and Wireless Components Letters, vol. 23, no. 12, pp. 683-685, December 2013) propose a DPD scheme capable of narrowing the bandwidth of the feedback path in which the AD converter is disposed in order to reduce the request for the AD converter for the purpose of reducing the cost of the distortion compensation apparatus.
NPL 4 propose, as shown in FIG. 1, a DPD scheme that can reduce the sampling frequency of the AD converter for the feedback path to 368.64 MHz by limiting the feedback signal for the output observation of the power amplifier to a narrow band of 100 MHz by a BPF (Band-Pass Filter) for an input signal having a modulation band of 100 MHz. However, in the technique disclosed by NPL 4, the DPD is operated at a sampling frequency of 3.68 times the band of the input signal.
On the other hand, for example, U.S. Pat. No. 9,209,753 proposes the Band-Limited Volterra Series-Based DPD scheme as means for reducing the sampling frequency of the AD converter for the feedback path, the DA converter for transmission, and the sampling frequency of the DPD for the purpose of further reducing the cost of the distortion compensation apparatus.
In the technique disclosed in U.S. Pat. No. 9,209,753, the DPD based on a Band-Limited Volterra Series model generates a distortion compensation signal for an input signal having a modulation band of 100 MHz. Further, distortion outside the band of the filter that limits the band of the distortion compensation signal generated by this DPD is suppressed by the BPF of the related art disposed at the output part of the power amplifier. U.S. Pat. No. 9,209,753 proposes the DPD scheme capable of reducing the sampling frequency of the DPD from 500 MHz of the related art to 200 MHz with this configuration. However, in the technique disclosed in U.S. Pat. No. 9,209,753, the DPD is operated at a sampling frequency twice the bandwidth of the input signal.
In the technique disclosed in U.S. Pat. No. 9,209,753, a non-linear processing unit is provided at an upstream of a bandwidth limitation unit that limits the band of the distortion compensation signal within a pre-set bandwidth. It is necessary for the non-linear processing unit to generate high order non-linear distortion and a high order memory effect for compensation, which has not yet been limited, to be output within the limited band based on a Volterra Series parameter. In order to do so, although the sampling frequency of the hardware of the non-linear processing unit is reduced to 200 MHz in the non-linear processing unit, a high-speed operation is required for a calculation processor of the non-linear processing unit (which is not explicitly described in U.S. Pat. No. 9,209,753, though). For example, assume that high order non-linear distortion and a high order memory effect that make the compensation performance within the limited band equal to the compensation performance at the 500 MHz sampling of the related art are generated. In such a case, it is necessary to operate a processor for non-linear processing calculation achieved by a microprocessor or an embedded processor such as a CPU at a frequency five times the band of the input signal.
Furthermore, U.S. Pat. No. 8,537,041 proposes a DPD subsystem that can improve a distortion compensation characteristic without increasing a sampling rate of an AD converter for a feedback path and a DA converter for transmission as compared with the related art.
The technique disclosed in U.S. Pat. No. 8,537,041 includes, in the DPD subsystem, a DPD main body, an interpolation circuit disposed as a Pre-DPD Processor at an upstream of the DPD main body, and a decimation circuit disposed as a post-DPD processor at a downstream of the DPD main body. With this configuration, the sampling rates of the input and the output of the DPD subsystem do not apparently change from those of the related art, and the sampling rates of the AD converter for the feedback path and the DA converter for the transmission can be made the same as those of the related art. However, as described above, the interpolation circuit is provided in the DPD subsystem in practice. Therefore, the technique disclosed in U.S. Pat. No. 8,537,041 is nothing other than a technique of operating the DPD main body at a sampling frequency twice the rate of the input signal even when an interpolation factor L is the lowest 2.
Moreover, it can be said that the technique disclosed in U.S. Pat. No. 8,537,041 is about a band-limiting DPD in which the processing, which is performed by the processor for non-linear processing calculation disclosed in U.S. Pat. No. 9,209,753 in order to limit the band after the high order non-linear distortion and the high order memory effect are generated in the technique disclosed in U.S. Pat. No. 9,209,753, is replaced with a hardware interpolation circuit and a decimation circuit.
As described above, for example, in order to perform distortion compensation on the input signal (baseband) in the 800 MHz band in the quasi-millimeter wave/millimeter wave band, the operating frequency of the DPD needs to be 1.6 GHz, which is twice the input signal band 800 MHz even in the technique disclosed in U.S. Pat. No. 9,209,753. Likewise, the operating frequency of the DPD needs to be 1.966 GHz, which is 2.4576 times the input signal band 800 MHz (the rate of the input signal 983.04 MHz×2) in the technique disclosed even in U.S. Pat. No. 8,537,041.
Next, in order to show the distortion compensation performance of the related art which is to be a reference, a distortion compensation characteristic of the upsampling distortion compensation apparatus shown in FIG. 8 including the 2× interpolation circuit 8 at the upstream of the DPD 1 for an input signal (=input signal rate 983.04 MHz) in the 800 MHz band in the quasi-millimeter wave/millimeter wave band will be described using a specific non-linear model of a power amplifier.
The input signal (the baseband signal) x(n) of the distortion compensation apparatus shown in FIG. 8 is upsampled by the interpolation circuit 8 at the upstream of the DPD 1, and the upsampled xu(n) is input to the DPD 1. The up sampling by the interpolation circuit 8 increases the sampling rate (the sampling frequency) of the input signal x(n) and expands the digital signal band for the distortion compensation in the DPD 1. In this example, the upsampling ratio by the interpolation circuit 8 is twice as high as the original sampling rate, and the operating frequency of the DPD 1 is set to the rate of the input signal of 983.04 MHz×2=1.96608 GHz. The operating frequency of the DPD 1 at this time is equal to 2.4576 times the band 800 MHz of the input signal x(n).
In the DPD 1, yu(n) is generated by adding in advance a signal having an inverse characteristic of the non-linear distortion of the power amplifier 4 to the input up sampled xu(n).
In the DPD 1, when the generalized memory polynomial structure is applied, the output signal yu(n) of the DPD 1 is a result of calculating the following equation (1) for the upsampled input signal xu(n) of the DPD 1.
                                          y            u                    ⁡                      (            n            )                          =                              ∑                          l              =                              -                                                      L                    -                    1                                    2                                                                    +                                                L                  -                  1                                2                                              ⁢                                    ∑                              k                =                0                                            K                -                1                                      ⁢                                                            x                  u                                ⁡                                  (                                      n                    -                    l                                    )                                            ·                              a                                  l                  ,                  k                                            ·                                                                                                            x                      u                                        ⁡                                          (                                              n                        -                        l                                            )                                                                                        k                                                                        (        1        )            
Here, a time shift amount 1 of a memory effect term in the equation (1) is a time shift amount (i.e., a sample shift amount) in the unit of a sampling cycle (=1/sampling frequency) of the output signal yu(n) of the DPD 1. Furthermore, in the generalized memory polynomial, the above-mentioned time shift amount for an input signal at a certain sample timing is generalized and expanded to not only a lagging term but also a leading term. For that reason, 1 can be any value from
      -                  L        -        1            2            to    ⁢                  +                            L          -          1                2            .      Note that L is referred to as a memory order or the number of memory taps. Thus, hereinafter, the time shift amount 1 of the memory effect term is referred to as a memory tap for convenience.
When the power series calculation for each term of the memory tap 1 in the equation (1) which is:
      ∑          k      =      0              K      -      1        ⁢            a              l        ,        k              ·                                                x            u                    ⁡                      (                          n              -              l                        )                                      k      is achieved by a power series function of:Kl(|xu(n−l)|)which is for an amplitude of each term of the memory tap 1 by a hardware LUT (Look Up Table) instead of a direct calculation by a calculation processor, the equation (1) can be expressed by the following equation (2).
                                          y            u                    ⁡                      (            n            )                          =                                            ∑                              l                =                                  -                                                            L                      -                      1                                        2                                                                              +                                                      L                    -                    1                                    2                                                      ⁢                                          ∑                                  k                  =                  0                                                  K                  -                  1                                            ⁢                                                                    x                    u                                    ⁡                                      (                                          n                      -                      l                                        )                                                  ·                                  a                                      l                    ,                    k                                                  ·                                                                                                                        x                        u                                            ⁡                                              (                                                  n                          -                          l                                                )                                                                                                  k                                                              =                                    ∑                              l                =                                  -                                                            L                      -                      1                                        2                                                                              +                                                      L                    -                    1                                    2                                                      ⁢                                                            x                  u                                ⁡                                  (                                      n                    -                    l                                    )                                            ·                                                K                  l                                ⁡                                  (                                                                                                        x                        u                                            ⁡                                              (                                                  n                          -                          l                                                )                                                                                                  )                                                                                        (        2        )            
In the term of l=0 in the equation (2), the time shift amount of the output signal of the DPD 1 for the input signal of the DPD 1 becomes zero. Thus, the polynomial at l=0 corresponds to a memoryless polynomial.
When, specifically, L=7 is given and the substitution is performed like l=ls−3 for the time shift amount 1 is in the equation (2), the equation (2) can be expressed by the following equation (3).
                                          y            u                    ⁡                      (            n            )                          =                                            ∑                              l                =                                  -                  3                                                            +                3                                      ⁢                                                            x                  u                                ⁡                                  (                                      n                    -                    l                                    )                                            ·                                                K                  l                                ⁡                                  (                                                                                                        x                        u                                            ⁡                                              (                                                  n                          -                          l                                                )                                                                                                  )                                                              =                                    ∑                                                l                  s                                =                0                            6                        ⁢                                                            x                  u                                ⁡                                  (                                      n                    +                    3                    -                                          l                      s                                                        )                                            ·                                                K                                      l                    s                                                  ⁡                                  (                                                                                                        x                        u                                            ⁡                                              (                                                  n                          +                          3                          -                                                      l                            s                                                                          )                                                                                                  )                                                                                        (        3        )            
When n in the above equation (3) is delayed by three samples, it can be expressed by the following equation (4).
                                          y            u                    ⁡                      (                          n              -              3                        )                          =                              ∑                                          l                s                            =              0                        6                    ⁢                                                    x                u                            ⁡                              (                                  n                  -                                      l                    s                                                  )                                      ·                                          K                                  l                  s                                            ⁡                              (                                                                                              x                      u                                        ⁡                                          (                                              n                        -                                                  l                          s                                                                    )                                                                                        )                                                                        (        4        )            
In the term of ls=3 (i.e., l=0) in the equations (3) and (4), the time shift amount of the output signal of the DPD 1 for the input signal of the DPD 1 becomes zero. Thus, the polynomial at ls=3 corresponds to the memoryless polynomial.
FIG. 10 shows a block diagram when the calculation of the above equation (4) in the DPD 1 according to the related art is achieved by, for example, a hardware function.
The DPD 1 in FIG. 10 achieves the calculation of the above equation (4). The DPD 1 in FIG. 10 includes one-sample delay devices 301a, 301b, 301c, 301d, 301e, and 301f, amplitude address calculation circuits 302a, 302b, 302c, 302d, 302e, 302f, and 302g, and LUTs (lookup tables) 303a, 303b, 303c, 303d, 303e, 303f, and 303g, complex multipliers 304a, 304b, 304c, 304d, 304e, 304f, and 304g, and an adder 305. The specific description of FIG. 10 is omitted.
When the equation (4) and the configuration of FIG. 10 are applied, assuming that the non-linear order is 0 to 7 and the memory order (the number of memory taps) is 7, it is necessary to derive the inverse system for 8×7×2=112 non-linear model coefficients as complex coefficients (of the I phase and Q phase).
In order to address the first problem in the related art in which an extensive amount of calculation is required, a method of expressing the seventh-order memory polynomial model achieving the above equation (4) and FIG. 10 by an approximate model that combines a three-tap polynomial and a 5-tap FIR filter is introduced to reduce the coefficient amount.
There is no example about the method based on this approximate model disclosed in the documents and the like regarding the related art. However, this method using the approximate model can be regarded as an extended configuration from the related art. The method using the approximate model includes three of the Wiener-Hammerstein models shown in FIG. 2(c) of NPL 1 connected in parallel.
The above equation (2) is transformed into an approximate model based on a combination of a polynomial having a reduced coefficient amount and the FIR filter, and is expressed by the following equation (5). In this equation, it is assumed that L (the memory order) is lower than 7 given by the equation (3) before the coefficient amount is reduced.
                                          y            u                    ⁡                      (            n            )                          =                              ∑                          l              =                              -                                                      L                    -                    1                                    2                                                                    +                                                L                  -                  1                                2                                              ⁢                                    ∑                              r                =                                  -                                                            R                      -                      1                                        2                                                                              +                                                      R                    -                    1                                    2                                                      ⁢                                          W                                  l                  ,                  r                                            ·                                                x                  u                                ⁡                                  (                                      n                    -                    l                    -                    r                                    )                                            ·                                                K                  l                                ⁡                                  (                                                                                                        x                        u                                            ⁡                                              (                                                  n                          -                          l                          -                          r                                                )                                                                                                  )                                                                                        (        5        )            
Like the above equation (2), in the terms of l=0 and r=0 in the equation (5), the time shift amount of the output signal of the DPD 1 for the input signal of the DPD 1 becomes zero. Thus, the polynomial at l=0 and r=0 corresponds to the memoryless polynomial.
When, specifically, L=3 taps and R=5 taps are given to the above equation (5) in order to reduce the coefficient amount, the equation (5) can be expressed by the following equation (6).
                                          y            u                    ⁡                      (            n            )                          =                              ∑                          l              =                              -                1                                                    +              1                                ⁢                                    ∑                              r                =                                  -                  2                                                            +                2                                      ⁢                                          W                                  l                  ,                  r                                            ·                                                x                  u                                ⁡                                  (                                      n                    -                    l                    -                    r                                    )                                            ·                                                K                  l                                ⁡                                  (                                                                                                        x                        u                                            ⁡                                              (                                                  n                          -                          l                          -                          r                                                )                                                                                                  )                                                                                        (        6        )            
Furthermore, when the time shift amount 1 is substituted as in l=ls−1, and r is substituted as in r=rs−2 for r, the equation (6) can be expressed by the following equation (7).
                                          y            u                    ⁡                      (            n            )                          =                              ∑                                          l                s                            =              0                        2                    ⁢                                    ∑                                                r                  s                                =                0                            4                        ⁢                                          W                                                      l                    s                                    ,                                      r                    s                                                              ·                                                x                  u                                ⁡                                  (                                      n                    +                    3                    -                                          l                      s                                        -                                          r                      s                                                        )                                            ·                                                K                                      l                    s                                                  ⁡                                  (                                                                                                        x                        u                                            ⁡                                              (                                                  n                          +                          3                          -                                                      l                            s                                                    -                                                      r                            s                                                                          )                                                                                                  )                                                                                        (        7        )            
When n in the equation (7) is delayed by 3 samples, it can be expressed by the following equation (8).
                                          y            u                    ⁡                      (                          n              -              3                        )                          =                              ∑                                          l                s                            =              0                        2                    ⁢                                    ∑                                                r                  s                                =                0                            4                        ⁢                                          W                                                      l                    s                                    ,                                      r                    s                                                              ·                                                x                  u                                ⁡                                  (                                      n                    -                                          l                      s                                        -                                          r                      s                                                        )                                            ·                                                K                                      l                    s                                                  ⁡                                  (                                                                                                        x                        u                                            ⁡                                              (                                                  n                          -                                                      l                            s                                                    -                                                      r                            s                                                                          )                                                                                                  )                                                                                        (        8        )            
In the terms of ls=1 (i.e., l=0) and rs=2 (i.e., r=0) in the equations (7) and (8), the time shift amount of the output signal of the DPD 1 for the input signal of the DPD 1 becomes zero. Thus, the polynomial at ls=1 and rs=2 corresponds to the memoryless polynomial.
FIG. 11 shows a block diagram when the calculation of the above equation (8) with the reduced coefficient amount in the DPD 1 is composed of, for example, a hardware function.
The DPD 1 in FIG. 11 achieves the calculation of the above equation (8). The DPD 1 in FIG. 11 includes one-sample delay devices 401a and 401b, amplitude address calculation circuits 402a, 402b, and 402c, LUTs 403a, 403b, and 403c, complex multipliers 404a, 404b, and 404c, an FIR filter0 405a and an FIR filter1 405b, an FIR filter2 405c, and an adder 406. Furthermore, each of the FIR filter0 405a, the FIR filter1 405b, and the FIR filter2 405c includes one-sample delay devices 411a, 411b, 411c, and 411d, complex multipliers 412a, 412b, 412c, 412d, and 412e, and an adder 413.
In FIG. 11, to make descriptions simple, the polynomial in which the coefficient amount is reduced in the outputs of the complex multipliers 404a, 404b, and 404c for each term of the memory tap ls of the above equation (8), which is:xu(n−ls)·Kls(|xu(n−ls)|)is substituted by the function du(n−ls) as shown in the following equation (9).xu(n−ls)·Kls(|xu(n−ls)|)=du(n−ls)  (9)
The one-sample delay devices 401a and 401b generate, from the up sampled input signal xu(n) of the DPD 1 at a certain sample timing, xu(n), xu(n−1), and xu(n−2) that are delayed each by one sample. The amplitude address calculation circuits 402a, 402b, and 402c calculate, for the respective signals of xu(n), xu(n−1), xu(n−2) that are delayed each by one sample, LUT amplitude addresses corresponding to the amplitudes |xu(n)|, |xu(n−1)|, and |xu(n−2)| of the respective signals. The LUTs 403a, 403b, and 403c are referred to based on the LUT amplitude addresses for the respective signals each delayed by one sample, and output signals of the respective LUTs corresponding to the LUT amplitude addresses are obtained. Then, the output signals of the respective LUTs are complex-multiplied by the respective signals each delayed by one sample by the complex multipliers 404a, 404b, and 404c. The results of the complex multiplications performed by the complex multipliers 404a, 404b, and 404c are input to the FIR filter0 405a, the FIR filter1 405b, and the FIR filter2 405c as the polynomial du(n−ls) with the reduced coefficient amount for each term of the memory taps ls=0, 1, and 2. The FIR filter0 405a corresponds to the memory tap ls=0. The FIR filter1 405b corresponds to the memory tap ls=1. The FIR filter2 405c corresponds to the memory tap ls=2.
The FIR filter0 405a, the FIR filter1 405b, and the FIR filter2 405c generate du(n−ls), du(n−ls−1), du(n−ls−2), du(n−ls−3), and du(n−ls−4), which are delayed each by one sample by the one-sample delay devices 411a, 411b, 411c, and 411d, from du(n−ls) input to the respective FIR filters. The complex multipliers 412a, 412b, 412c, 412d, and 412e complex-multiply the respective signals each delayed one sample by the filter (complex) coefficients Wls,0, Wls,1, Wls,2, Wls,3, and Wls,4 corresponding to the FIR taps rs=(0, 1, 2, 3, 4), respectively. After that, the signals complex-multiplied by the complex multipliers 412a, 412b, 412c, 412d, and 412e are added by the adder 413. The signal added by the adder 413 is output from the FIR filter0 405a, the FIR filter1 405b, and the FIR filter2 405c as:
      ∑                  r        s            =      0        4    ⁢            W                        l          s                ,                  r          s                      ·                  d        u            ⁡              (                  n          -                      l            s                    -                      r            s                          )            for each memory tap ls.
The output signal of the filter0 405a corresponding to the memory tap ls=0 is as follows.
      ∑                  r        s            =      0        4    ⁢            W              0        ,                  r          s                      ·                  d        u            ⁡              (                  n          -                      r            s                          )            The output signal of the FIR filter1 405b corresponding to the memory tap ls=1 is as follows.
      ∑                  r        s            =      0        4    ⁢            W              1        ,                  r          s                      ·                  d        u            ⁡              (                  n          -          1          -                      r            s                          )            The output signal of the FIR filter2 405c corresponding to the memory tap ls=2 is as follows.
      ∑                  r        s            =      0        4    ⁢            W              2        ,                  r          s                      ·                  d        u            ⁡              (                  n          -          2          -                      r            s                          )            
The output signals of the FIR filter0 405a, the FIR filter1 405b, and the FIR filter2 405c are eventually added by the adder 406, and the added signal is output from the DPD 1 as the polynomial in which the coefficient amount is reduced expressed by the above equation (8).
When the equation (8) and the configuration of FIG. 11 are applied, assuming that the non-linear order is 0 to 7, the memory order (the number of memory taps) is 3, and the number of FIR taps is 5, the inverse system for (8+5)×3×2=78 non-linear model coefficients may be derived as the (I phase and Q phase) complex coefficients. Thus, it is possible to reduce the coefficient amount by 30% compared with the case when the above-described equation (4) and configuration of FIG. 10 are applied (where the coefficient amount is 112).
The (8×3×2=48) power series coefficients and the (5×3×2=30) tap coefficients of the FIR filter0 405a, the FIR filter1 405b, and the FIR filter2 405c in the LUTs 403a, 403b, and 403c are derived as follows. That is, these power series coefficients and tap coefficients in the LUTs 403a, 403b, and 403c are derived by performing adaptive control with a ratio of an RMSE (Root Mean Square Error) of the input signal xu(n) in the feedback signal zu(n) of N samples to an RMS (Root Mean Square) value of the input signal xu(n) of the N samples of the DPD 1, which is to be a reference, as an error evaluation function.
As shown in the following equation (10), the above error evaluation function is an NRMSE (Normalized Root Mean Square Error), and is equivalent to an EVM (Error Vector Magnitude) of the feedback signal zu(n) for xu(n).
                              N          ⁢                                          ⁢          R          ⁢                                          ⁢          M          ⁢                                          ⁢          S          ⁢                                          ⁢          E                =                              20            ·                                          log                10                            ⁡                              (                                                                                                                              ∑                                                      n                            =                            1                                                    N                                                ⁢                                                                                                                                                                                                          z                                  u                                                                ⁡                                                                  (                                  n                                  )                                                                                            -                                                                                                x                                  u                                                                ⁡                                                                  (                                  n                                  )                                                                                                                                                                          2                                                                    N                                                                                                                                                    ∑                                                      n                            =                            1                                                    N                                                ⁢                                                                                                                                                                        x                                u                                                            ⁡                                                              (                                n                                )                                                                                                                                          2                                                                    N                                                                      )                                              =                      10            ·                                          log                10                            (                                                                    ∑                                          n                      =                      1                                        N                                    ⁢                                                                                                                                                                z                            u                                                    ⁡                                                      (                            n                            )                                                                          -                                                                              x                            u                                                    ⁡                                                      (                            n                            )                                                                                                                                      2                                                                                        ∑                                          n                      =                      1                                        N                                    ⁢                                                                                                                                    x                          u                                                ⁡                                                  (                          n                          )                                                                                                            2                                                              )                                                          (        10        )            
Next, the distortion compensation characteristic of the upsampling distortion compensation apparatus based on the interpolation circuit to which the above equation (8) and the configuration of FIG. 11 are applied for a specific non-linear model coefficient of the power amplifier is confirmed.
In this example, narrowing the channel bandwidth and increasing the number of carriers to aggregate to thereby increase a signal envelope change will be considered. Thus, a signal with a sampling frequency of 983.04 MHz, which is an aggregation of 10 carriers each having a channel bandwidth of 80 MHz with a sub-carrier spacing (SCS) of 60 kHz and the number of sub-carriers of 1200, is assumed as a signal having the system band of 800 MHz assumed in the quasi-millimeter wave/millimeter wave band. This signal shall be the input signal x(n) of the distortion compensation apparatus before being upsampled by the interpolation circuit 8 in FIG. 8. Further, the upsampling ratio by the interpolation circuit 8 is twice as high as the original sampling rate, and the upsampled signal input to the DPD 1 shall be xu(n). Furthermore, the operating frequency of the DPD 1 shall be 1.96608 GHz which is twice the rate 983.04 MHz of the input signal x(n).
As a specific non-linear model coefficient of the power amplifier, a power amplifier model coefficient by GaN (Gallium Nitride: Gallium nitride) for 28 GHz that is close to the above condition of the sampling frequency from among the generalized memory polynomial coefficients described by NPL 2, and in which the input/output data at the time of measuring the model is collected at the sampling rate of about 2 GHz is used. Commonly, the memory tap in the memory polynomial model is measured at the operating frequency (=the sampling rate) of the DPD employed, and the time shift amount of this memory tap is the time shift (sample shift) amount in units of the sampling cycle (=1/sampling rate) at the time of the measurement. This is because the sampling rate of the input/output data at the time of model measurement is an important index for selecting the number of memory taps (or the memory order) required for the DPD compensating the model.
First, FIG. 12 shows the distortion characteristic of the power amplifier model output for the interpolated upsampling signal when the DPD is not operated.
In the example of FIG. 12, the input signal x(n) having the system band of 800 MHz at the sampling frequency of 983.04 MHz is upsampled by a factor of 2 to make it 1.96608 GHz by the interpolation circuit 8. The characteristic shown in FIG. 12 is the output distortion characteristic of the power amplifier alone when this signal xu(n) upsampled by a factor of 2 is directly input, without operating the DPD, i.e., the above xu(n), to the generalized memory polynomial model of the power amplifier.
Under the operating condition of an output backoff of 9 dB, distortion outside the carrier band specified by the ACLR becomes lower than 28 dBc. However, an error from a carrier signal due to the distortion within the carrier band is higher than the out-of-band distortion by 5-10 dB. Thus, the compensation amount necessary for suppressing the distortion within the carrier band to the above-mentioned distribution target of 40 dBc that satisfies the EVM standard at 256 QAM is about 20 dB or more.
FIG. 13 shows the compensation characteristic by the upsampling DPD according to the related art.
In the example of FIG. 13, the input signal x(n) having the system band of 800 MHz at the same sampling frequency 983.04 MHz as that in FIG. 12 is upsampled by a factor of 2 to make it 1.96608 GHz by the interpolation circuit 8 at the upstream of the DPD 1. The signal xu(n) upsampled by a factor of 2 is used as the input signal of the DPD 1. The above equation (8) and the configuration of FIG. 11 are applied to perform adaptive control using the above equation (10) as the error evaluation function to operate the DPD 1. The characteristic shown in FIG. 13 is the distortion compensation characteristic by the double upsampling DPD in which the above coefficient amount is reduced by 30% obtained by inputting the output signal yu(n) of the DPD 1 at this time to the generalized memory polynomial model of the power amplifier.
With the double upsampling DPD, an error from a carrier signal due to distortion within a carrier band can be suppressed to an average value of 48.4 dBc as compared with an average value of 23.6 dBc when the DPD shown in FIG. 12 is not operated.
As described above, in order to address the first problem in the related art in which an extensive amount of calculation is required, the upsampling distortion compensation apparatus by the interpolation circuit to which the above equation (8) and the configuration of FIG. 11 are applied to reduce the coefficient amount may be introduced. According to the upsampling distortion compensation apparatus using this interpolation circuit, the coefficient amount can be reduced by 30% as compared with the DPD to which the above equation (4) and the configuration of FIG. 10 according to the related art are applied. Further, according to the upsampling distortion compensation apparatus using this interpolation circuit, as shown in FIG. 13, it can be seen that compensation performance for achieving the above target can be obtained both outside and within the carrier band.
However, in the upsampling distortion compensation apparatus using the interpolation circuit to which the equation (8) and the configuration of FIG. 11 are applied, as described above, the system requirement for the operating frequency of the DPD 1 exceeds the performance trend of an achieved device, because the interpolation circuit 8 at the upstream of the DPD 1 upsamples signals by a factor of 2 to make it 1.96608 GHz. For this reason, the above-mentioned second problem remains unsolved.
FIG. 14 is a block diagram of a distortion compensation apparatus in which the interpolation circuit 8 shown in FIG. 8 is deleted, and the upsampling for the DPD is not performed in order to address the second problem concerning the device performance in the distortion compensation apparatus according to the related art.
A difference between a configuration of FIG. 14 and that of the previously described FIG. 8 is that the input signal x(n), which has not been upsampled for the DPD along with the deletion of the interpolation circuit 8, is directly input to the DPD 1. Further, another difference between the configuration of FIG. 14 and that of FIG. 8 is that the sampling frequencies of the output signal y(n) and the input signal x(n) of the DPD 1 are the same, although the DPD 1 adds in advance a signal having an inverse characteristic of the non-linear distortion of the power amplifier 4 to the input x(n) to generate y(n) and outputs it.
With the configuration shown in FIG. 14, the operating frequency of the DPD 1 for the band 800 MHz of the input signal x(n) in the quasi-millimeter wave/millimeter wave band is 983.04 MHz, which is necessary for processing baseband input signals in the 800 MHz band, because the upsampling for the DPD is not performed. For this reason, the ratio of the operating frequency of the DPD 1 to the band of the input signal x(n) is 1.2288, which is less than that of the related art where the ratio of operating frequency of the DPD 1 to the band of the input signal x(n) is two.
Next, the problem in the distortion compensation apparatus having the configuration of FIG. 14 in which the interpolation circuit 8 is deleted, and the upsampling for the DPD is not performed will be described. The input signal x(n) in the 800 MHz band and the output signal y(n) of the DPD 1 in FIG. 14 are signals sampled at a sampling frequency of 983.04 MHz. The maximum frequency of the amplitude envelope change in the input signal x(n) having a modulation band of 800 MHz is 800 MHz. However, when the maximum frequency of the amplitude envelope change in the input signal x(n) is close to the sampling frequency, a change in the amplitude envelope of the signal interpolated by the interpolation DA converter 2 becomes deviated from a change in the amplitude envelope of the signal before interpolation.
FIG. 15 shows a comparison between an amplitude change of a signal in the 800 MHz band at the sampling frequency of 983.04 MHz before the interpolation and an amplitude change of a signal obtained by up sampling this signal by a factor of 2 through the 2× interpolation processing to make it 1.96608 GHz. Note that the 2× interpolation processing is performed by the first stage 2× interpolation circuit in the above-described interpolation DA converter 2 shown in FIG. 9 in which zero-stuffing is performed on an input signal, and then an image is eliminated by a half-band filter for interpolation.
The above 2× interpolation generates interpolated sample points between sample spacing of the signal before the interpolation. However, there are samples in which the amplitude envelope change of the double-interpolated signal largely deviates from the amplitude envelope change between the samples in the signal before the interpolation (in FIG. 15, the samples largely deviating are surrounded by double broken lines).
Next, FIG. 16 shows a comparison between an amplitude change of a signal upsampled by a factor of 2 to achieve the sampling frequency of 1.96608 GHz through the 2× interpolation processing and an amplitude change of a signal obtained by upsampling this signal by a factor of 4 to achieve the sampling frequency of 3.93216 GHz through another 2× interpolation processing. Note that the 2× interpolation processing added for upsampling the signal by a factor of 4 is performed by the 2× interpolation circuit at the downstream in the interpolation DA converter 2 shown in FIG. 9.
There is no big difference between the amplitude envelope change of the double-interpolated signal and the amplitude envelope change of the signal after 4× interpolation.
As described above, when the maximum frequency of the amplitude envelope change is close to the sampling frequency (e.g., the ratio of the sampling frequency to the input signal band is less than 2), it can be seen that the change in the amplitude envelope of the interpolated signal deviates from the change in the amplitude envelope of the signal before the interpolation.
As described above, when the interpolation circuit is deleted, and the upsampling for the DPD is not performed, there is a problem that the amplitude envelope change of the signal interpolated by the interpolation DA converter 2 at the downstream of the DPD 1 deviates from that of the signal before the interpolation to be processed by the DPD 1. It is unnecessary to consider this problem in the distortion compensation apparatus that employs the upsampling DPD 1 by interpolation according to the related art for upsampling a signal by a factor of 2 at the upstream of the DPD 1. This problem is to be solved only in the distortion compensation apparatus in which the upsampling for the DPD is not performed.
In FIG. 14, the DPD 1 generates the output signal y(n) of the DPD 1 having the same sampling frequency as that of the input signal x(n) by the input signal x(n) having the sampling frequency of 983.04 MHz and the feedback signal z(n). However, an envelope of a modulated signal input to the power amplifier 4 is equal to an envelope of a modulated signal converted into an analog signal after y(n) is interpolated by the interpolation DA converter 2. Therefore, in order to compensate the distortion occurring in the power amplifier 4, in particular, it is necessary to consider the sample points interpolated by the interpolation DA converter 2 to compensate the memory effect affected by the sample before and after a certain sample point. However, this interpolated sample point cannot be reflected in the distortion compensation signal for compensating the memory effect, because this sample point is a sub-sample point interpolated between sample points for the DPD 1 operating at the sampling rate before the interpolation.
The above problems will be described in detail. The memory tap in the equation (8) and the memory tap in the configuration of FIG. 11 for performing the upsampling by a factor of 2 for the DPD are the sample shift amount by the unit of the sampling cycle (=1/sampling frequency) after upsampling a signal by a factor of 2 to make it 1.96608 GHz at the upstream of the DPD 1. Therefore, for example, the memory tap ls=1 in the above equation (8) is a memory tap of a sub-sample corresponding to the memory tap=0.5 for the DPD 1 operating at the sampling frequency of 983.04 MHz in the configuration shown in FIG. 14 in which the interpolation circuit is deleted, and the upsampling for the DPD is not performed. Therefore, the memory tap ls=1 cannot be reflected in the distortion compensation signal that compensates the memory effect, because it is not a memory tap target for the DPD 1 operating at the sampling frequency of 983.04 MHz.
As described above, when the configuration in which the interpolation circuit at the upstream of the DPD is deleted, and the upsampling for the DPD is not performed is employed, and when the DPD is operated at a sampling frequency 1.2288 times the input signal band 800 MHz, it is difficult for the DPD and the distortion compensation apparatus according to the related art to achieve target compensation performance.